1.Introduction
The FPICST04-ADC is a high-performance ADC expansion module designed for FPGA development boards that support the FPIC (FPGA Peripheral Interface Connector) standard. The module provides a flexible and modular solution for integrating high-speed analog-to-digital conversion capabilities into FPGA-based data acquisition and signal processing systems.
The FPICST04-ADC module supports two ADC variants to address different sampling-rate requirements:
- ADC3664 – High-Speed Variant(125 MSPS): Designed for high-speed data acquisition applications requiring higher sampling rates and increased data throughput.
- ADC3661 – Low-Speed Variant(10 MSPS): Intended for applications with lower sampling-rate requirements while maintaining the flexibility of the same expansion module platform.
The module interfaces with the FPGA development board through the standardized FPIC connector, providing the necessary electrical connections for ADC data transfer, clocking, configuration, and control signals. This standardized interface enables compatibility with supported FPGA platforms without requiring board-specific modifications to the ADC module.
2.Applications
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High-speed analog data acquisition.
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Real-time digital signal processing.
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Analog waveform monitoring and analysis.
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FPGA-based test and measurement systems.
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Communication signal acquisition and processing.
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Industrial sensor monitoring.
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Continuous analog data logging.
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FPGA-based embedded data acquisition systems.
3.Features
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Dual ADC Support: Accommodates ADC3664 (high-speed variant) and ADC3661 (low-speed variant).
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FPIC ST Interface: Provides a standardized FPIC connector for interfacing with compatible FPGA boards.
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Dual Analog Input Channels: Supports two independent analog input channels (CH-A and CH-B).
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SMA Connectors: Provides dedicated SMA connectors for analog signal inputs.
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LVDS Data Interface: Supports LVDS outputs for high-speed ADC data transfer to the FPGA.
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SPI Configuration: Enables ADC configuration and control through the SPI interface.
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Clock Generation: Incorporates the SI5340A clock generator for generating the required ADC sampling and digital clock signals.
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I2C Interface: Provides I2C communication between the FPGA and the clock generator.
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EEPROM Support: Includes an onboard EEPROM for module identification and configuration information.
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Modular Design: Enables integration with compatible FPGA platforms through the standardized FPIC interface.
4.Functional Block Diagram

5.Connection Diagram
6.Connection Details
| SL No. | Signal | FPIC Pin Location | Signal Detail |
|---|---|---|---|
| 1 | DCLK_P | IO0_P/CLK0_P | ADC Data Clock+ → FPGA |
| 2 | DCLK_N | IO0_N/CLK0_N | ADC Data Clock- → FPGA |
| 3 | FCLK_P | IO1_P/CLK1_P | ADC Frame Clock+ → FPGA |
| 4 | FCLK_N | IO1_N/CLK1_N | ADC Frame Clock- → FPGA |
| 5 | DA0_P | IO2_P | ADC Channel A Data Lane 0+ |
| 6 | DA0_N | IO2_N | ADC Channel A Data Lane 0- |
| 7 | DA1_P | IO3_P | ADC Channel A Data Lane 1+ |
| 8 | DA1_N | IO3_N | ADC Channel A Data Lane 1- |
| 9 | DB0_P | IO4_P | ADC Channel B Data Lane 0+ |
| 10 | DB0_N | IO4_N | ADC Channel B Data Lane 0- |
| 11 | DB1_P | IO5_P | ADC Channel B Data Lane 1+ |
| 12 | DB1_N | IO5_N | ADC Channel B Data Lane 1- |
| 13 | SDIO | IO6_P | ADC SPI Data I/O |
| 14 | SEN | IO6_N | ADC SPI Chip Select (CS) |
| 15 | SCLK | IO7_P | ADC SPI Clock |
| 16 | SDI | IO7_N | ADC SPI Data Input |
| 17 | PDN/SYNC | IO8_P | ADC Power-Down / Synchronization Control |
| 18 | RESET | IO8_N | ADC Reset Control |
| 19 | CLOCK_SCLK | IO9_P | Clock Generator I²C SCL |
| 20 | CLOCK_SDA | IO9_N | Clock Generator I²C SDA |
| 21 | GA0 | GA0 | EEPROM Address Select GA0 |
| 22 | GA1 | GA1 | EEPROM Address Select GA1 |
| 23 | SCL | SCL | EEPROM I²C SCL |
| 24 | SDA | SDA | EEPROM I²C SDA |
7.Technical Specification
| SL No. | Parameter | Value | Unit |
|---|---|---|---|
| 1 | Module Name | FPICST04-High Speed & Low Speed ADC Module | |
| 2 | ADC Support | ADC3664 / ADC3661 | |
| 3 | ADC Channels | 2 (CH-A, CH-B) | Channels |
| 4 | Analog Input Connector | SMA | |
| 5 | Connector Standard | FPIC-ST | |
| 6 | ADC Data Interface | LVDS | |
| 7 | ADC Configuration Interface | ||
| 8 | Clock Generator | SI5340A | |
| 9 | Clock Generator Interface | I²C | |
| 10 | EEPROM | 24AA025E64T-I/SN | |
| 11 | EEPROM Capacity | 2 | Kbit |
8.ADC Variant Specifications
| SL No. | Parameter | ADC3664 (High-Speed) | ADC3661 (Low-Speed) | Unit |
|---|---|---|---|---|
| 1 | ADC Resolution | 14 | 16 | Bits |
| 2 | Maximum Sampling Rate | 125 | 10 | MSPS |
| 3 | Number of Channels | 2 | 2 | Channels |
| 4 | Digital Output Interface | Serial LVDS | Serial LVDS |