AMD Kintex Ultrascale FPGA Board

The Neutron KU60 Development Board is a multi-FPGA platform designed to support flexible system configuration, control, and high-speed inter-device communication. In the Neutron architecture, the Kintex UltraScale FPGA (XCKU060-1FFVA1517I) serves as the high-performance processing device, while the Spartan-7 FPGA (XC7S50-1CSGA324C) is used for system management and configuration control (system controller).

The on-board Spartan-7 FPGA functions as the system controller for SelectMAP-based configuration of the Kintex UltraScale KU60 FPGA. It operates in SelectMAP master mode, managing the parallel configuration interface  and generating the configuration clock (CCLK).

The SelectMAP configuration interface is a parallel configuration mode used for programming AMD FPGAs, enabling high-throughput bitstream transfer under external master control. In this configuration scheme, the Spartan-7 FPGA operates as the configuration master, controlling the configuration sequence, while the Kintex UltraScale FPGA functions as the slave device, receiving configuration data and control signals through the SelectMAP interface.

This diagram illustrates the master-slave configuration relationship where Spartan-7 controls KU60 programming through a dedicated 8-bit/16-bit parallel bus with key control and status signals.

In the Neutron KU60 FPGA development board, the Spartan-7 FPGA operates as the system controller and SelectMAP master, responsible for configuring the Kintex UltraScale KU60 FPGA.

The configuration is performed using the SelectMAP interface in parallel mode (e.g., x8 & x16mode), where the Spartan-7 generates the configuration clock (CCLK) and drives the data bus. It controls configuration signals such as PROGRAM_B and monitors INIT_B and DONE to manage and verify the configuration process.

The Spartan-7 reads the configuration bitstream from onboard memory and transfers it to the KU60, ensuring proper sequencing and error handling during configuration.

In the Neutron KU60 development board, the KU60 FPGA is configured using the SelectMAP interface, where the Spartan-7 FPGA acts as the configuration master and the KU60 operates as the slave device. The configuration bitstream (.bin file) for the KU60 is pre-stored in the QSPI flash memory connected to the Spartan-7.

The configuration process is initiated by the Spartan-7 through a bootloader application developed in Vitis. This application reads the bitstream data and its size from the external memory and prepares the SelectMAP interface for data transfer. The KU60 configuration logic is first reset by asserting the PROGRAM_B signal, and the interface control signals such as RDWR_B (set to write mode) and CSI_B (chip select) are configured accordingly. The system then waits for the INIT_B signal from the KU60 to go High, indicating that the device is ready to receive configuration data.

Once initialization is complete, the Spartan-7 begins transferring the bitstream to the KU60 over the parallel SelectMAP data bus. The data is sent sequentially in synchronization with the configuration clock (CCLK), ensuring proper timing and reliable communication. During this phase, the INIT_B signal is continuously monitored to detect any configuration errors that may occur while transmitting the bitstream.

After the complete bitstream has been successfully transmitted, additional clock cycles are provided to finalize the startup sequence. The DONE signal from the KU60 is then monitored to confirm successful configuration. A High state on the DONE signal indicates that the FPGA has been properly programmed and is ready for normal operation. This SelectMAP-based approach enables efficient, high-speed configuration of the KU60 FPGA under the control of the Spartan-7 master device.

Step 1:

In Vivado, open the Generate Memory Configuration File utility from:

Tools → Generate Memory Configuration File

Step 2:

Select the file Format as BIN and choose the exact SPI Flash Memory Part used in the design. Provide a suitable name for the output file.

Enable Load bitstream files and add the generated download.bit file. Place the SelectMAP bootloader bitstream at the required flash start address and allocate the application BIN/bitstream file to a different flash location with sufficient reserved memory space.

Check Disable bit swapping, as this setting is mandatory for proper SelectMAP data transfer.

Step 3:

Verify all the settings and click OK or Generate to create the BIN file for the SelectMAP-based FPGA configuration.

Quad SPI NOR flash memory device (MT25QL256ABA8E12-0AAT) is connected to the Spartan 7 FPGA, with a capacity of 256 Mbit.
The flash memory operates at 3.3 V and is used for FPGA configuration storage and non-volatile data storage.

The Spartan 7 FPGA has a Push-button SW6, typically used as a “Reset” signal for designs running on the FPGA. Push-button SW6 is connected to FPGA pin T12. Push-button SW6 is active-high. This pushbutton can also be used for any other input and is not just limited to being used as a Reset signal.

The Spartan-7 System Controller is provided with a dedicated 200 MHz differential system clock (P: D14, N: D14). This clock ensures stable and reliable operation of the system controller functions, including FPGA configuration and system management tasks.

The board uses an FTDI FT4232HL USB interface device.
Channel B of the FTDI is configured as a UART interface, and the associated signal connections are listed below.

Contact us for more details about the system controller.