Getting Started With Zynq on Styx using Vivado Design Suite

November 29, 2016


Vivado Design Suite by Xilinx is used for synthesis and analysis of HDL designs with additional features for SoC development and high-level synthesis. Xilinx recommends use of Vivado Design Suite for new designs with Ultra scale, Virtex-7, Kintex-7, Artix-7, and Zynq-7000. In this article we will use Vivado to create a basic “Hello World” program for Styx Zynq Module running on Zynq’s ARM processor. We will also demonstrate use of EMIO for routing peripheral signals to programmable logic.

Styx Zynq Module

Styx Xilinx Zynq FPGA Module

Styx Zynq Module is the first product from Numato Lab featuring Zynq-70xx SoC. Styx is pin-compatible with Numato Lab’s Saturn Spartan 6 FPGA module, Neso Artix 7 FPGA module and Skoll Kintex 7 FPGA module and allows for seamless upgrade in most cases. Styx offers built in USB 2.0 interface that can be used to program the board as well as do debugging or data transfer with the host.

Styx Zynq Module  features a Zynq 7020 from Xilinx in CLG484 package. The unique feature of Zynq-7000 series is that they are complete System on Chip (SoC) with an FPGA die which makes it a very powerful combination. Zynq 7020 has dual-core ARM Cortex A9 and a whole bunch of peripherals which are typically found in SoCs. Additionally, it has Artix-7 equivalent programmable logic section, connected to SoC using AXI interconnects. This SoC + FPGA combination makes Zynq very flexible for multitude of uses. With Zynq 7020 on board, Styx is a great choice for learning, product development and OEM integration.


To follow this article, you would need the following:

  • Hardware:
    1. Styx Zynq Module
    2. Xilinx Platform Cable II JTAG debugger.
  • Software:
    1. Xilinx Vivado Suite
    2. FT_Prog tool for configuring on-board FT2232H USB Serial converter (download and install from FTDI website)

Let’s get started

The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with Zynq processing system using IP integrator. This article is written for Numato Lab’s Styx Zynq Module, but can be adapted to any other Zynq based platform with minor changes. Screenshots are added wherever possible to make the process easier to the reader.

Step 1:

Download and install Vivado Board Support Package files for Styx from here. Follow the readme in the link on how to install Vivado Board Support Package files for Numato Lab’s boards.

Step 2:

Start Vivado Design Suite, and select “Create New Project” from Quick Start section. The project wizard will pop up.  Press next to proceed with creating the project.


Step 3:

Type in a project name and save it at a convenient location. For this example “styxHello” is used as project name, but feel free to use any name. Select the check box below to keep all project files in a single folder. The image below shows the settings for the example project. Click “Next” to continue.


Step 4:

Choose “RTL Project” as project type and check the option “Do not specify sources at this time”.


Step 5:

At the “Default Part” step, select “Boards” and choose Vendor as “”. Select “Styx” and click “Next”. If Styx is not displayed in the boards list, you will need to install Styx board support files correctly. Please refer to this readme on how to install Vivado board support package files for Numato Lab’s boards.


Continue the wizard and finish creating the project. When the new project wizard exits, a new project will be opened up in Vivado with the settings you have selected.

Step 6:

Under Flow Navigator, select “Create Block Design” in IP Integrator. Give an appropriate name to design. We will call it “styx” for example.


Step 7:

Go to Diagram window, right click and select “Add IP” from the popup menu. Search for ZYNQ7 Processing System. Add it to block design by double clicking.


Step 8:

Click on “Run Block Automation” option on the green bar.


Step 9:

In the “Run Block Automation” window, select the options as in image below and click OK.


Step 10:

The Zynq IP block will have changed after running block automation. Right click on “UART_0” port of the Zynq IP block and select “Make External”.


Step 11:

Now we have to add constraints for the external UART_0 port. In the Sources window, right-click anywhere and select “Edit Constraints Sets”. Add a new constraints file, paste the code below and save the file with a convenient name.

Step 12:

Go to “Sources” tab, right click on “styx” design file and select “Create HDL Wrapper”. Click OK on the window that appears to finish generating wrapper.


Step 13:

Click “Generate Bitstream” and click “Yes” in any subsequent dialog window which comes up.



Step 14:

Once the bitstream is successfully generated, close any “Bitstream Generation Completed” dialog which comes up asking for what to do next.


Go to File -> Export -> Export Hardware…


Check “Include bitstream”, keep “Export to:” default, and click OK.



Finally click File -> Launch SDK.

Step 15:

After Xilinx SDK windows opens, Go to File -> New -> Application Project


Step 16:

Type in a project name, leave other options as default and click “Next”. In the next window, select Hello World template and click “Finish”.



Step 17:

Once the project is created, SDK will automatically run a build. If that didn’t happen for any reason, run a build manually. Once the build is complete successfully, power up Styx Zynq Module and connect Xilinx Platform USB cable and Micro USB cable for Serial debugging to the board. Make sure to configure channel B of the onboard FT2232H USB – Serial device as virtual communication using FT_Prog. The process is very similar to that of Saturn and details are available here. Change the Styx’s Boot Mode to JTAG. Please refer to user manual to learn more about configuring Styx’s Boot Mode.

Step 18:

Program the board by selecting Xilinx Tools -> Program FPGA. Click Program in the window that opens up.


Step 19:

Open any serial terminal program (such as PuTTY, Teraterm etc) and open the port corresponding to Styx’s Channel B at 115200 baudrate.

Step 20:

After FPGA is successfully programmed, right click on the executable .elf file of our Hello World program, go to Run As -> Launch on Hardware (System Debugger), as shown in image below:


If everything went well, the application running on the board should print “Hello World” over the UART and should be displayed on the Serial Terminal application.






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